I want to finally understand how to compile in C well, any resource recommendations?

I don't know much about writing makefiles, and I'm sure someone will come by later and give a more comprehensive and sensible answer, but what I'd suggest is keep it simple stupid. Start off with a blank makefile, learn the basics, and then focus on gcc flags where the real meat and potatoes is.

For the most part I'm happy just doing gcc -O2 -j8 foo.c where my CPU has 8 threads. This will compile with optimization level 2 (faster to execute, slower to compile), and 8 threads. If I know I'm going to be running the binary on the current CPU I'm using I'll add -march=native or if I know it'll be run on a different, but still modern CPU I'll do something like -march=skylake to enable support for things like SSE4 or AVX or whatnot.

In a makefile, to keep things neat and maintainable you'll want to put these into variables at the top of the file. You'll want to put those compiler options into a CFLAGS variable, and your source files into another variable, etc, like so:

CC = gcc
CFLAGS = -O2 -j8 -march=native
SOURCES = foo1.c foo2.c 
OBJECTS = foo1.o foo2.o

Or if you want to compile all the C files in the current directory you could do like SOURCES=$(wildcard *.c)

Then further down you'd use a syntax like this to use your variables:

program: $(OBJECTS)
     $(CC) $(CFLAGS) $(OBJECTS) -o program

The makefile mostly just says what input files you want to compile, and what options you want the compiler to use. If you are targeting a specific distro you can write up an install target to tell it where to put the resulting binaries, etc. The meat and potatoes of optimizing compilation comes down to which CFLAGS you give gcc.

The comprehensive and exhaustive documentation for gcc can be found here. While doing surface level research for this reply I found this basic makefile tutorial here, another surface level tutorial here, and a good list of optimizations for gcc here.

Is your goal to better understand Makefiles, compiler and linkers, or just know how to make stuff work without needing to tinker with it for a long time?

Personally, and I'm sure this is blasphemy to some people, I'm not interested in writing Makefiles. I just want my stuff to work and hand-writing Makefiles is rarely the most efficient path to getting there for me. This is probably biased by that I rarely create projects targeted at only one OS, and almost never targeted at only one compiler. Because of this I instead favor abstraction tools. I'd rather use something like add_dependency(foo bar) from CMake to have "foo" take a dependency on "bar" than to need to manually set the right flags on the compiler and linker to get header paths and object files imported correctly. Usually, though admittedly not always, these abstractions provide far better names than the flags they get transformed to which can make them easier to understand. It also means that if my project gets big enough that parallel building with an automatically generated dependency graph becomes worth it I can usually just change that tool from targeting make to ninja.

If you want to keep with Makefiles or learn them in depth then what I said is not helpful at all. For that my advice would be to start a Makefile from scratch. Don't copy anything in at all. From there, go bit by bit manually putting in just the exact targets you want and the command line strings you want to be executed. It won't be pretty, but you'll understand it. Then, once you understand what each thing is doing, start adding prerequisites, then variables, then branches, then wildcards, and so on. Basically, start by treating it like its no more than a collection of .sh files (ex. put what you'd want to put into clean.sh into clean:) and then slowly use more Makefile features only when you're sure why you're doing it. I'd start with something as bland as

program:
	gcc main.c -o program

then

program: main.c
	gcc main.c -o program

and so on. Because Makefiles really don't have a ton of features you're likely to need immediately you will likely have a pretty solid handle on what the Makefiles themselves are doing after a few iterations. Then you need to dive into the documentation of your preferred compiler and linker for figuring out the flags and such. If you want a specific resource https://makefiletutorial.com/ seems fine at describing the concepts, although I wouldn't try to follow it like a tutorial but would instead just read through what it says about each concept (targets, prereqs, variables, etc.) and apply them as needed.

The core functionality of make is simple and very general, extending beyond C and software development: given a target file, its prerequisite files and a recipe that generates the target, it runs the command only if any of the prerequisite files are newer than the target. Rules can be dependent: if the target of one rule is a prerequisite of another rule, it'll evaluate the former rule first.

For make, I like the Introduction to Makefiles in the GNU Make manual.

For the compiler front-end, there are a lot of flags and options for more or less obscure use cases, so it really depends on what you do. The GCC manual provides a helpful summary. Most importantly I think, you pass -c to tell the frontend to compile the given source files into an object file without linking it. You pass -o with a name to specify an output name. I usually pass -Wall -O3 when compiling to enable all warnings and a high degree of optimization respectively. For linking to system libraries I use pkg-config to generate the appropriate flags to the linker and compiler.

So for a simple single-file C application, in the shell I might invoke

cc -Wall -O3 $(pkg-config --cflags libpcap) -c application.o application.c # compile into object file
cc application.o $(pkg-config --libs libpcap) -o application # link into executable.

The corresponding Makefile might be something like

application: application.o
    cc -Wall -O3 $(shell pkg-config --cflags libpcap) -c application.o application.c

application.o: application.c application.h
    cc application.o $(shell pkg-config --libs libpcap) -o application

or, because GNU make has pre-defined implicit rules for these things based on a set of variables

CFLAGS += -Wall -O3 $(shell pkg-config --cflags libpcap)
LDLIBS += $(shell pkg-config --libs libpcap)

application: application.o
application.o: application.c application.h

Note that the Makefile only really shines when you are linking multiple independent object files. Then, if you have specified the dependencies correctly, it'll only recompile the objects to which the dependencies have changed, and relink, saving you a whole lot of compilation of source files that haven't changed.

In addition to the great info in the comments here, I'd like to share this old topic from 2018:

How do I hack makefiles?

There was also another topic about makefiles posted earlier this year:

Be aware of the Makefile effect

But I haven't read it yet