IBM claims world’s first sub-1 nanometer chip technology

More descriptively, this is the world's first "vertically staggered transistor microprocessor architecture." FinFETs already have vertically stacked channels on any given transistor, but N-type and P-type transistors still couldn't be too close because of their polarity. There wasn't room to shrink the gap between them any further. It seems like IBM's new CFET arrangement increases density without physically reducing component size by simply arranging the transistors in a novel way.

The "sub-nanometer" designation is confusing to me because it seems not to refer to anything physical on the chip, but rather serves as a proxy for some other space efficiency improvement. I originally learned that an xx-nanometer chip measurement referred to the half-pitch between two transistor gates. However, for at least the last 20 years, I don't think 16nm, 14nm, 7nm, etc. technology has measured that. As the article says:

But keep in mind that such node numbers have nothing to do with the actual physical dimensions of IBM’s chip features. Older generations of chips developed in the 1970s and 1980s had physical features with dimensions matching the number in the name of their chip technology’s node or process—such as chips made at the 180-nanometer node—but that has not been the case for decades and certainly not for the latest chip generations made with a 3-nanometer or 2-nanometer process.

Instead, IBM is basically claiming that its new “nanostack” architecture can deliver the computing performance improvements that would be expected if a theoretical chip could be built with physical features smaller than 1 nanometer.

So why even headline the nanometer milestone? I would rather hear about the physical changes to the architecture. IBM's design is a fascinating implementation of long-awaited design ideas, but this theoretical comparison is an unhelpful abstraction.

I appreciate the value of a standardized compute indicator, like a "tons of CO2-equivalent gas" metric in environmental emissions, but just as that example downplays the ratio/potency of CH4, the "sub-nanometer" term subsumes the amazing three-dimensional advancements being made here into a flat model. Vertical transistor stacking surely has its own unique efficiency characteristics and manufacturing quirks. I suppose we can smush it all into a "nanometer-equivalent" measurement, but it changes the way we think about the devices on a granular scale and the velocity of efficiency gains we can anticipate in future production contexts.

Maybe the nanometer terminology conveys the general necessary meaning (a generational change in processor speed), but it means people are less likely to engage with the real innovation happening here, and they might not anticipate future processing capabilities with as much accuracy.

Perhaps I'm asking for too much. Of course I understand that narratives (not features) make products, and people are already familiar with this nanometer progression arc. Storytelling is part of the bridge between the technical and the practical. I just find it silly to use the explicitly pre-loaded technical language of measurement instead of highlighting a separate marketing concept to fit the new architecture. "Sub-1 nanometer" is contextless and misleading. "Nanostack" is halfway to usefulness. I'm sure we can find a great replacement if we try!